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大家好，同样一块板子，第一次artwork时没有问题，第二次增加了两侧的工艺边后，artwork是报错，Dbcheck不通过，然后进行database check 一下为database的描述：" p9 x$ S1 ?6 V/ U% I
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& [! T1 L% j l+ O' F( ]0 v6 u* PeRFormance checking for design Z:/E/supcon/PRD-13002/hardware/ESP-300 V1.1/ESP-300 V1_1.brd
2 O- U, U" ^6 [9 |********************************************************************************: i$ F+ a# S% h. J K
4 k' Z. q! X0 k5 w$ |' a0 \/ V
Ratsnest schedule check' u. H2 m/ C6 z& T
-------------------------------1 Q4 k* B) f: J/ S& a: ^! A
* OK.+ Z5 }( ^5 i) y E
$ u( `) j, f" h& SDRC check
' r# U4 i& J+ e----------------------
9 K5 j9 g% \9 I% J* The number of physical/spacing csets is 0.060241 larger than the number
$ m; q5 W) m7 J! j of nets Suggest examining constraint model.
' Y8 T( v( Q+ X6 A" m8 j! L ISSUE: Misuse of the allegro constraint model such as using a spacing6 L0 p* S0 ]: F" K
cset for each diffpair in the design. Result is system/ y: F1 f# d9 l l1 R( _8 F: g
performance degradation.% C( S; Y1 P% ], c) Z2 }: A# ]
$ ~8 M T: o) |) L5 T
# q+ z- ?8 k( w7 j$ P( fConstraint region check
# x$ f$ `* c# G- ^-------------------------------+ }, y/ ?+ ^2 Y& q" Q
* Region on all - MINIUSB: Suggest use by layer or outer/inner regions.
, K6 ], R8 N, ?6 L" }" X) m ISSUE: Encourage use of new layer based regions which helps performance and
& ? h& T* D5 ~% H; G simplifies constraint management., G# M! d/ W. O1 _" ] y9 y" P% M
: O7 r0 l+ I" A5 i; z* F' v. c
* o- p2 f' \' u& F/ F# M8 ~" J$ r shape/region location: (35.1028,-31.5976)7 [8 B$ i" I/ {) @1 ?( w. h2 T
class: CONSTRAINT REGION subclass: ALL7 `* R. k- R# R1 C l4 R
. l0 C9 X: A% P* l6 Y: W2 \* Region on all - CPU: Suggest use by layer or outer/inner regions.! U, M/ u/ ]) m' \4 n
ISSUE: Encourage use of new layer based regions which helps performance and7 [& n8 v# _0 {3 l
simplifies constraint management.9 [0 e- G% n' Z+ [8 [" h4 G+ }
" A8 }! d5 t& ~ ?) }, d
1 b7 t7 r$ v4 }; k. h shape/region location: (7.9883,19.2659)2 s( n/ v _3 y, L9 s6 _# } l
class: CONSTRAINT REGION subclass: ALL' ] f* x) q ^1 i7 L
1 z4 y/ q7 l/ B$ A# U# M8 @9 E
. R, e& z. @7 u @0 R8 b7 z, sDynamic shape check
+ [; a+ c& E! o" Z: d- b-------------------------------/ @; O: K; e& b; m6 K: j
* OK.
7 s# r& s3 ?2 b- |/ b
1 x$ u% p( U0 |- XSector table check
: u/ V1 a" U R$ Q$ j3 m" Q0 x-------------------------------
5 F' b9 M5 k2 e0 y- z* The ratio of design extent to route keepin extent is too large (10.375068). Suggest reducing design extent.
5 k, V0 E0 U# e# T3 t' J& n; M8 ?+ G' m# E; u G) U1 q
Constraint set check
, }7 X+ b; Y# [7 V1 j---------------------------------
* O0 s2 ^' o8 D. l# h1 ~* Unused csets list (4):+ K* i, K( g& e+ H
ISSUE: Design maintenance issue, slight performance impact.
# ?: r1 J+ z: l3 O& n+ I/ v4 g* q
0 s: s0 |* S g: d" F5 f. P SNCS: SN-POW3 N0 U* c) b5 ^; H! F# _) \* g/ b7 a
PCS: PHY-LCDBG
0 H1 g, ?8 T- |" s( B& I PCS: PHY-POW
( }, x7 [6 c3 l) j; m SCS: SCSET-POW
5 p/ L, U' ^! `6 O6 Y, t6 P$ m7 c9 {% i6 b
( D H* a6 V( g7 R$ @" P2 WNODRC_SYM_SAME_PIN check
1 N3 `* ?; s5 C9 A---------------------------------% i8 N P' e. z. |& Y& I
* OK.& j5 H% C$ s; e8 k# B# _
$ C7 F. H) F- W* f
Cross section check for bad dielectric constant values1 f/ g' n: z- h9 T8 y8 V
--------------------------------------------------------
5 N9 V. X V: @% q9 ?5 L- Y; A! S* OK.
$ K$ u" `) t# n; f0 c& L; d8 m+ h/ U
padstack size check+ Y! a' ` S: ~' ^
---------------------------------
+ y/ T0 _* u6 v; r% U' r% s* OK.
! T. T0 C- @. O2 X8 D
1 L' a4 B. f* E" U" t# K1 h! y8 j2 X+ y5 Y
4 problems found. 1 maintenance problems found.7 g, f9 U- \7 V
# R0 k- @6 u# c2 v$ W. ^
* Z; G/ A( a) h# {* B7 O问题：
/ ~+ P6 J* I6 m( Z1、artwork时是否有勾选实时数据检查；$ Z1 ?; o z# t. X3 u/ @6 C5 [
2、database check中哪些可以忽略，甚至屏蔽；# ^& K5 _2 e) m; d2 Z
还有相关问题可提出，望大家一起，群策群力！！！! K6 R6 J1 h* H
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发表于 2013-6-20 08:51
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支持！
反对！