|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
cadence SPB16.6下载(Hotfix013已发布)
5 s6 B5 ]/ {6 e! r) Y j" v% k \2 s8 d: _7 I2 f. I w
Cadence SPB16.6已经推出，需要的朋友可以点击下面的链接下载：
, L5 J9 L4 t2 i/ s6 jhttp://dl.vmall.com/c0ych9k8m39 f" y8 I* A( m w% }
f' i$ t; V4 b2 z0 y- N
DATE: 07-26-2013 HOTFIX VERSION: 013
# C) W# T/ s* i* {, @6 k7 P=================================================================================================================================== R1 u6 n( V5 J
CCRID PRODUCT PRODUCTLEVEL2 TITLE- F8 U# C5 _* T9 J
===================================================================================================================================
7 S3 g( H5 s" l0 n; Q111368 CAPTURE CORRUPT_DESIGN Capture - will not produce allegro netlistwith 10.0, O! I& q) h- S$ v/ h2 T2 k) v
134439 PD-COMPILE USERDATA caCell terminals should be top-levelterminals4 J: Z0 q# l. {! U
186074 CIS EXPLORER refresh symbols from lib requires youto close CIS8 S* c# F2 R# C0 o/ r
583221 CAPTURE SCHEMATIC_EDITOROption to have the Schematic Page Name as a Property in the Titleblock1 F4 ], \2 X5 N! O8 T
591140 concept_HDL OTHER Scale overall output size inPublishPDF from command line
& J) m7 _( O0 Q% A4 _801901 CONCEPT_HDL CORE Concept Menus use the same key"R" for the Wire and RF-PCB menus8 K3 V6 D' g. A
813614 APD DRC_CONSTRAINTS With Fillets present the "cline toshape" spacing is wrong.
! w2 A$ T0 v1 S/ F! n. C881796 ALLEGRO_EDITOR GRAPHICS Enhancement request for Panning with Middle Mouse Button
# g' [+ F/ v+ V" q887191 CONCEPT_HDL CORE Cannot add/edit the locked property3 o: C! H" _1 c3 X7 g6 h4 r2 M6 y
911292 CONCEPT_HDL CORE Property command on editing symbolattaches property to ORIGIN immediately
) s$ Z6 z2 N, a O5 \- C987766 APD SHAPE Void all command gets result as novoids being generated on specific env.' q% a) d, K% S0 K5 |5 u
1001395 SIP_LAYOUT ASSY_RULE_CHECK Shape Minimumvoid check reports lots of DRCs which are not necessary to check out.: W: p( b, |- X9 p1 k6 a0 K. S
1030696 ALLEGRO_EDITOR INTERACTIV Enh - Allow another behavior of PANmovement using middle mouse in Allegro
; `& u5 M# j1 q0 l5 T1043856 ADW TDA Diff between TDOand DE-HDL Hierarchy Viewer is confusing to the user& _# u, [! H, T; a3 H8 R, I: G, A
1046440 ADW PCBCACHE ADW: ImportSheetis not caching libraries under flatlib/model_sym when the source design is notan ADW project, ~0 y) N. S) x
1077552 F2B PACKAGERXL Diff Pairs get removed when packing withbackannotation turned on
- N( k0 E/ R: R2 N) z$ H% B1079538 F2B PACKAGERXL Ability to blockall 縮ingle noded nets� to the board while packaging.
6 B; Q; X. a7 h0 g5 v1086362 ALLEGRO_EDITOR SHAPE Enhancement request to autovoid a viaif shape cannot cover the center of the via.4 Y! S3 S8 P7 m
1087958 Pspice MODELEDITOR Is there anylimitation for pin name definition?
, e1 w& e+ P$ x& Z1087967 CIS UPDATE_PART_STAT Update part status window shows incorrect differences! k' h) i9 @7 T4 n& I$ H* z
1090693 ADW LRM LRMauto_load_instances does not gray out Load instances Button
3 I2 o. S$ b! b5 k1 c1097246 CONCEPT_HDL CORE ConceptHDL -assign hotkeys to alpha-numerical keys
* f0 B5 s9 a1 X( [9 |; i6 l" C1099773 CONCEPT_HDL CORE DE HDL goes intorecursive loop if a custom text locked at site level is deleted from Tools >Option
" q4 u. O% X" x3 I1100945 SCM SCHGEN SCM generatedDE-HDL has $PN placement issue- q0 o, l; h( _8 A; a8 z5 [
1100951 PSPICE SIMULATOR Increasing theresolution of fourier transform results in out file
' V3 O6 J# I z4 E* a3 }1103117 RF_PCB FE_IFF_IMPORT Enh- Allow theAllegro_Discrete_Library_to_ADS_Library_Translator to output in its originalunit: r' o) x, I. Q7 M. Z
1105473 PSPICE PROBE Getting errormessages while running bias point analysis." F/ c- i! O( b8 z, v- a: C
1106116 FLOWS PROJMGR view_pcb settingchange was cleared by switching Flows in projmgr.
* Q( j1 G: o0 ]1106298 ALLEGRO_EDITOR INTERACTIV Copy Shape uses last menu pick locationas origin and not the Symbol Origin as specified in Options.
6 e5 e& f8 p; I# p% } f# |1106626 CONCEPT_HDL CORE Concept HDL crashes when saving pages; z( k0 z" ^4 N7 n, Y
1107086 ALLEGRO_EDITOR INTERACTIV manual void with arc's goes in wrongdirection during arc creation
! B: ?) Q9 g$ h3 G1107172 CONCEPT_HDL OTHER Project ManagerPackager does not report errors on missing symbol
0 X8 y. v/ s1 h( A1108193 CONCEPT_HDL CORE Using theleft/right keys do not move the cursor within the text you're editing
8 O, f' ^; G" V5 L& w1108603 PCB_LIBRARIAN VERIFICATION PDV ToolsVerification > View Verification (CheckPlus) leaves<project>.cpm_tmp.cpm" a! r8 \4 x5 B+ R7 y/ r
1109024 CIS OTHER orcad performance issue from Asus.4 P4 Z$ l% f! U1 `9 U; U# M
1109109 CAPTURE NETLIST_ALLEGRO B1: Netlistmissing pins when Pack_short property pins connected
/ r1 h _# |! t! H2 K/ }1109466 ALLEGRO_EDITOR ARTWORK Artwork create some strange gerberlines for fillet.5 W% \0 N% {8 h4 o
1109647 SIP_LAYOUT DEGASSING Shape degassingcommand enhancement - control over what layers are counted in even/odd layersets.
g' x( C5 _ r$ Z1109926 CONCEPT_HDL CORE viewing a designdisables console window
0 f& q- d9 }/ A& S' l1110194 SIP_LAYOUT WIREBOND If OpenGL settings for display ofdynamic net names is enabled, should be visible while push/shove wirebonds.* K6 k& ^$ e, y$ F
1112357 SIP_LAYOUT WIREBOND wirebond commandcrashes the application) A4 }5 R$ U* b; }0 Y3 n: |) N; X
1112395 CONCEPT_HDL CORE 縗BASE\G� for global signal is not obeyedafter upreving the design to 1650.% A; R; V- n' J
1112658 CAPTURE PROPERTY_EDITOR Changing Part 縂raphic� value from property EditorChanges Occ refdes values to instance4 s9 ]4 G. l0 h/ `5 w' t$ A
1112662 CAPTURE PROJECT_MANAGER Capture crashesafter moving the library file and then doing Edit> Cut( I3 ^$ w! I5 p8 x2 M
1113177 PCB_LIBRARIAN CORE Pin Shapes arenot getting imported properly
" R3 d1 X5 l' P$ F9 k" i1113380 ALLEGRO_EDITOR INTERACTIV Change layer to - option for packagetype .dra is not available in 16.6 release
5 |1 N, Q2 C( Q4 }" }1113656 SIP_LAYOUT WIREBOND Enable Changecharacteristic to work without unfixing its Tack point.7 c0 p3 r+ |5 \ y
1113838 SIP_LAYOUT DIE_ABSTRACT_IF probe pinsdefined in XDA die abstract file are added with wrong location4 L" ]7 v8 h1 l) K9 E$ X
1113991 CAPTURE GENERAL Save Project Asis not working if destination is a linux machine9 ?, g7 E& O5 |* O! ?9 M! Z$ U: j
1114073 APD DRC_CONSTRAINTS Shape voidingdifferently if there are Fillets present in the design.
/ P+ ~9 U3 h% c# g1114241 CAPTURE SCHEMATIC_EDITOR Port not retaining assigned color, when moved on theschematic5 N; g; m, L; G9 B2 v! O
1114442 PSPICE PROBE Getting Internalerror - Overflow Convert with marching waveform on. D4 n9 ]( E+ Z% A
1114630 CONCEPT_HDL ARCHIVER Archcore failsbecause the project directory on Linux has a space in the name: d6 A! z2 @' K/ Z
1114689 CONCEPT_HDL CORE Unknown projectdirective : text_editor4 \; I$ J6 F7 z0 r4 a$ p4 x$ \
1114928 F2B PACKAGERXL 縀rror (SPCODD - 5) while Export Physical even afterchange pin from A<0> to A: ]& p1 G' V C" s2 j; E
1116886 CONCEPT_HDL CORE Crefer hyperlinksdo not work fine when user use double digits partitions for page Border.
2 m0 o5 x' [4 f1118088 ALLEGRO_EDITOR EDIT_ETCH Should Plan accurate and Optimize beremoved in 16.6?
; N' B& u B- t( }1118734 APD EDIT_ETCH Multiline routingwith Clines on Null Net cannot route in downward direction9 Y! C7 _( `% N9 [) g+ t( G" t6 o
1118756 ALLEGRO_EDITOR SHAPE Shape clearance parameter oversizevalues getting applied to Keepouts
6 S7 Z* g, p3 A8 r* ^ v, O1 b/ f1119606 CONCEPT_HDL MARKERS Filtering two ormore words in Filter dialog box
! _0 Y) w$ B" m# j1119707 CONCEPT_HDL CORE Genview does not use site colors when gen schfrom block symbol8 \3 w% W6 u' M
1119711 F2B DESIGNSYNC DesignDifferences show Net Differences wrongly3 t- d" q0 v7 r; }
1120659 CAPTURE PROJECT_MANAGER "Saveproject as" does not support some of Nordic characters.
# z: s2 P8 F! U% q, k1120660 CONCEPT_HDL CORE Save hierarchysaves pages for deleted blocks.
; {/ ?! O; u1 r9 ~ E$ v5 J1120817 SIP_LAYOUT SYMB_EDIT_APPMOD Rotate pads commands not working while in the SymbolEdit App. mode8 b( Y' W) J- A& v
1120985 PSPICE MODELEDITOR Unable to importattached IBIS model
7 q2 ]; {5 g. E6 d9 b1121171 CONCEPT_HDL CREFER PNN and correctproperty values not annotated on the Cref flat schematic
) a: p# m9 H W( M3 \" J3 O8 |1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change aftersaving and reopening.) S& y, c# M) ] @) K3 h0 w
1121382 ALLEGRO_EDITOR INTERACTIV Undo command is limited to two for thisdesign& t1 Q9 e! M( z
1121540 F2B PACKAGERXL pxl.chg keepsdeleting and adding changes on subsequent packager runs
! M. M! N9 P; |* C& A6 |1121558 ALLEGRO_EDITOR MODULES Unrouted net and unrouted connectionwhen module is placed of completely routed board file.
( |( s+ k2 ~$ H, f. _+ K* d* s1121585 ALLEGRO_EDITOR OTHER Drill Hole to Shape Same NetSpacing with Dynamic Shapes shows wrong result.
z9 I a& Y' M4 C, B9 \1121651 CAPTURE SCHEMATIC_EDITOR "PCB editor select" menu option is missing/ r; Z. T6 g8 y, X9 D5 t, i
1122136 SIP_LAYOUT PLACEMENT Moving acomponent results in the components outline going to bottom side of the design.
- y& c }, W$ v# S# i1122340 CAPTURE NETLIST_ALLEGRO Cross probe ofnet within a bus makes Capture to hang.
Y! }, _3 {( K+ T' B9 o" i1122489 CONCEPT_HDL OTHER Save _Hierarchycausing baseline to brd files
" ]7 T' e0 b' x- @1122781 CONCEPT_HDL CORE cfg_package isgenerated for component cell automatically; @9 h- d, M" m6 Z1 K# w5 [, p& N0 S
1122909 CONCEPT_HDL CORE changing versionreplicates data of first TOC on 2nd one
. n2 w3 m2 P$ k! W( x6 M' Q6 K8 Q0 }1123150 CONCEPT_HDL CORE property on yaxis in symbol view was moved by visibility change to None.
3 [% Y) M0 W2 z5 B$ {9 x1123176 ALLEGRO_EDITOR UI_FORMS Negative values for pop-up location isnot retained with multiple monitors (more than 2)
! r" V8 G. N, M6 [$ ^# E# N1123815 ALLEGRO_EDITOR GRAPHICS Embedded netname changes to a differentnetname: P* ?6 w0 }1 B4 z& L( ^7 [0 o
1124369 ALLEGRO_EDITOR INTERACTIV Sliding a shape using iy coordinate doesnot work indepedent of grid.
! z9 B/ r2 ^7 D- I1124544 CONCEPT_HDL CORE About SearchHistory of find with SPB16.5
: F' K, B0 T# H: B+ i$ ]$ _1124570 APD IMPORT_DATA When importingStream adding the option to change the point) F/ }8 W& l' l7 l( L* I' y
1125201 CONCEPT_HDL CORE Connectivityedits in NEW block not saved( lost) if block is created using block add. u2 k, H9 C* t4 d8 s
1125314 ALLEGRO_EDITOR INTERACTIV Enved crash during setting of library paths inuser preference
0 C- A5 n# X) h+ W8 A6 ]( Y1125366 CONCEPT_HDL CORE DE-HDL crachESDuring Import Physical if CM is open on Linux
) i- ]1 k- y5 y! p" s1125628 CONCEPT_HDL CORE Crash on doingsave hierarchy. M- e% ?: d( H. {5 _8 x: i
1130555 APD WIREBOND Wirebond Import should connect to pinsof the die specified on the UI.5 W, e' n2 W5 @4 s& h
1131030 PSPICE ENVIRONMENT Unregistered iconof Simulation setting in taskbar/ z9 `) N$ N, ]9 c1 v+ ^4 X$ O$ V1 {
1131083 ALLEGRO_EDITOR INTERACTIV Bug: 16.6 crash in changing the mode inFind filter window
3 r( L; [8 m( ]+ h* L1131226 ALLEGRO_EDITOR PLACEMENT When Angle is set in design parameterswhile placement component is rotated but outline is not.
3 t( z; D6 Z* d1 L1131567 CONCEPT_HDL OTHER Lower case valuesfor VHDL_MODE make genview use pin location to determen direction.
) j4 g+ Q/ Y: N1 P! G, K6 {1131699 PSPICE PROBE Probe windowcrash on trying to view simulation message
) A: K$ U! E9 W+ r1132457 CONCEPT_HDL CORE The schematicnever fully invokes and has connectivity errors.: v3 ]3 B6 u1 Z. b: b
1132575 CONCEPT_HDL CORE 2 pin_name weredisplayed and overlapped by spin command.
: V! o' K O) J1132698 ALLEGRO_EDITOR EDIT_ETCH Slide Via with Segment option with newSlide command
! [* Q) M. ]$ r1132964 ALLEGRO_EDITOR SHAPE Same net "B&B via toshape" errors created when adding shape
+ X' S( ^: H9 T. R7 a) r1133677 CONCEPT_HDL CORE Cant delete norreset LOCATION prop in context of top
% Y8 L0 U, v7 T- o1133791 CONCEPT_HDL CORE Cant do textjustification on a single selected NOTE in Windows mode.' Y$ q8 K) t+ l0 Z
1134761 CONCEPT_HDL CORE Why does MousePointer/Tooltip display LOCATION instead of $LOCATION property$ l9 n5 a, X% W/ a E7 \
1135118 ALLEGRO_EDITOR INTERACTIV Mirror and other editing commands aremissing for testpoint label text in general edit mode.
. r0 r- X. n0 _3 ]5 v; h2 a% i1136420 CAPTURE GENERAL Registrationissue when CDSROOT has a space in its path
+ T. w! s5 o8 y1136808 PSPICE STABILITY Pspice crashmarker server has quite unexpectedly
$ [) \! v: g+ ?8 T1136840 CAPTURE SCHEMATICS Enh: Alignment oftext placed on schematic page
% F7 i$ g9 `9 D& M! E, y7 k- I u1138586 ADW MIGRATION design migrationdoes not create complete ptf file for hierarchical designs
3 \' J& U+ Z$ A1139376 CONCEPT_HDL CORE setting wirecolor to default creates new wire with higher thickness" j4 [5 e3 }" h \2 m: U1 L
1140819 APD GRAPHICS Bbvia does notretain temp highlight color on all layers when selected.
. A3 e# B! Y" N: H; g7 @1141300 CONCEPT_HDL CORE DE HDL hier_writesave hierarchy log reports summarizes Successfully saved block x while blockwas skipped
& _2 Y2 o! M+ s6 v" v' y( q1141723 ADW PURGE purge commandcrashes with an MFC application failure message
" h6 o! ^3 L/ v8 f1143448 CAPTURE GENERAL About copy &paste to Powerpoint from CIS
' O C7 F' I+ `8 ?/ a8 q% K9 x1143670 SIP_LAYOUT OTHER Cross Probingbetween SiP and DEHDL not working in 16.6 release
! A* P) b! b7 D0 _/ v0 C$ n1143902 ALLEGRO_EDITOR DATABASE when the shape is rotated 45 degreesthe void is moved.1 d8 |' A& R X9 [% l2 w$ `/ I
1144990 PCB_LIBRARIAN CORE PDV expand &collapse vector pins resizes symbol outline to maximum height
( e/ C# t% F- F4 L% y5 l1145112 CONCEPT_HDL CORE Warning message:Connectivity MIGHT have changed
8 v4 f' U9 h9 m. G# P( \1145253 CONCEPT_HDL CORE Component Browseradds properties in upper case
) T i# i/ E c- ~: }9 G1146386 ALLEGRO_EDITOR INTERACTIV Place Replicate Create add Static shapewith Fillet shape
+ Y. F0 A" R; _3 P2 f1 ?1146728 F2B PACKAGERXL DCF with upperand lower case values on parts causes pxl to fail
3 U1 Y! f# x: c) ^6 ?$ |1146783 ALLEGRO_EDITOR INTERFACES Highlighted component is missing fromexported IPF file.' m0 z# I$ f# b+ Z7 r' [& e7 {
1147326 CONCEPT_HDL CORE HDL crashes whentrying to reimport a block/ H s$ J% Z. M" z5 K2 D
1148337 CAPTURE ANNOTATE Checking "refdes control" isnot giving the proper annotation result3 U; |6 i- C! s6 m3 x0 e6 Q& T& R8 P6 n
1148633 SIP_LAYOUT INTERACTIVE Add "%"to the optical shrink option in the co-design die and compose symbol placementforms% ^. s7 a& q" u$ q9 n- h' N" Y
1149778 CAPTURE SCHEMATICS Rotation of pspice marker before placementis not appropriate) U) ]1 G; c7 n5 L
1149987 PCB_LIBRARIAN PTF_EDITOR Save As pushingthe part name suffix into vendor_part_number value
1 ~& j& q0 X; l1151748 ALLEGRO_EDITOR OTHER If the pad and cline are the samewidth don't report a missing Dynamic Fillet.
, N2 A% Q7 o) M& r4 o8 _1152206 CONCEPT_HDL CORE ROOM Propertyvalue changes when saving another Page4 y' w, V; j' O5 @ M( F! h2 w) p. o
1152755 CONCEPT_HDL COPY_PROJECT Copy projecthangs if library or design name has an underscore
. d5 J/ u. m$ b7 e; Q7 I$ n1152769 PSPICE ENCRYPTION Unable to simulate Encrypted Models in16.65 Q; B6 m3 ~) q5 D
1153308 ALLEGRO_EDITOR DRC_CONSTR Creating Artwork Getting Warning"DRC is out of Date" even when DRC is up to date' I: D' E) s5 f- R" o
1153893 F2B DESIGNVARI 16.6 VariantEditor not supporting - in name
* h! p* r/ \* H9 t" {* s0 j1154185 SIG_INTEGRITY SIGNOISE Signoise didn'tdo the Rise edge time adjustment.
) G4 `" Z3 M2 [7 z: q& c+ e1154860 ALLEGRO_EDITOR MANUFACT Double digit drill character overlapswith figures triangle, hexagon and octagon in NC drill legend/ }+ y3 T: N, h5 g) ~. \: z8 ^/ Z
1155167 ALLEGRO_EDITOR EDIT_ETCH Via structure placed in Create Fanouthas incorrect rotation. U! c; E( _8 t* |/ d+ D+ R+ R. I
1155728 CONCEPT_HDL CORE Unable to uprevpackaged 16.3 design in 16.5 due to memory# i+ k( s- z- o6 f
1155855 SCM SCHGEN A newlyuser-defined net property is not transferred from SCM to DEHDL in PreservedMode
4 G: u4 N" n" ~ _7 k$ l1156274 ALLEGRO_EDITOR INTERFACES Exported Step file from Allegro is wrong( H& H* Z* g8 B: q9 ?2 v) v
1156316 CONSTRAINT_MGR OTHER Break in functionality whilecreation of pin-pairs under Xnet in Constraint Manager& Y- B/ d; D& _ ~1 `2 n5 m
1156351 CONCEPT_HDL CONSTRAINT_MGR Loose members inPhysical Net Class between DEHDL and Allegro
+ N/ g. |" b5 I" t0 M1156547 ALLEGRO_EDITOR DRC_CONSTR Etch Turn under SMD pin rule checkthrough pin Etch makes confused.& t5 ^9 U0 h4 |+ i1 D
1156779 CONSTRAINT_MGR OTHER Electrical Cset References in CM notworking correctly
* c2 q! M6 {; A8 i1 B7 g1157167 ALLEGRO_EDITOR skill axlPolyFromDB with ?line2poly isbroken, g8 F! l$ T+ x, r
1158042 ALLEGRO_EDITOR DFA DFA_DLG writes the dra file namein uppercase.
7 P8 {! X! D% ~1 }5 b; `! f" V1158718 CONCEPT_HDL CHECKPLUS Customer couldnot get $PN property values on logical rule of CheckPlus16.6.
2 }1 {4 S. R% |+ q1158970 ALLEGRO_EDITOR SCHEM_FTB Changing LOCATION to $LOCATION in DEHDLdoes not update the .brd file
8 _3 i- u- ^! a+ f1158989 ALLEGRO_EDITOR INTERFACES pdf_out -l creates a PDF) d0 R" A6 j$ z, V q7 Z, l9 \
1159285 APD DXF_IF DXF_OUT fails;some figures are not exported
! e, t4 S- u$ j) p1159432 ALLEGRO_EDITOR SHOW_ELEM http:// in the Show Element in 166 donot have HTML link to open the Website, ?1 {4 Z* T7 v$ B
1159483 PCB_LIBRARIAN SETUP part developercrashing with
: I+ A. f" ~& q1159516 ALLEGRO_EDITOR EDIT_ETCH Unable to slide cline segment with newslide.
2 [1 d4 x |" }4 N1159959 ALLEGRO_EDITOR GRAPHICS 3D viewer displays clines arcsincorrectly+ S) d6 U' f5 X$ r' }( h& t/ s
1160004 SCM UI The RMB->Pastedoes not insert signal names.8 S! z( n" O @$ B' f
1160410 ALLEGRO_EDITOR DATABASE Lock databse with View Lock option ismisleading7 }+ `. f; Q! E9 q5 }! {' c! V
1160529 SCM SCHGEN Schematicgeneration stopped because the tool was unable to create an appropriateinternal symbol structure1 g; k* b* k3 F& z6 Z x. x
1160537 SPIF OTHER Cannot start PCBRouter6 Y4 ^- F$ Y6 N1 b2 P' r
1161363 ALLEGRO_EDITOR SYMBOL Getting error SPMHGE-73 when tryingto mirror symbol% j1 ~/ x R7 d2 w
1161781 CONSTRAINT_MGR CONCEPT_HDL SigXp crash when selecting ECset indesign* f6 C. o, |+ M2 n+ X W/ C
1161896 ALLEGRO_EDITOR DRAFTING Tolerance value added for Dimensionsis not working correctly (HF11-12)- p: B4 x/ k4 ]( |9 j% N/ h9 ?
1162193 SIP_LAYOUT DIE_ABSTRACT_IF shapes in diafile not linked to the die after edit co-design die
( S: X. F4 A; }( a6 t8 d- x1162754 APD VIA_STRUCTURE Replace Via Structurecommand selecting dummy nets. |
|
/1 
发表于 2013-8-5 10:07
收藏
淘帖
支持！
反对！