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cadence SPB16.6下载(Hotfix013已发布)
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! J0 t. F7 C p8 x# i& @4 |Cadence SPB16.6已经推出，需要的朋友可以点击下面的链接下载：
. u& d) K0 c& T6 U) Qhttp://dl.vmall.com/c0ych9k8m3' m9 o4 ]4 M8 r0 o+ g) |% R1 L
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DATE: 07-26-2013 HOTFIX VERSION: 0133 l4 I) c; }. m
===================================================================================================================================! v k6 n/ r9 p9 c
CCRID PRODUCT PRODUCTLEVEL2 TITLE
# f+ |6 m. m0 g- @: n$ X===================================================================================================================================5 `; b+ Y5 T4 J$ |1 a. X
111368 CAPTURE CORRUPT_DESIGN Capture - will not produce allegro netlistwith 10.0 Y+ F" H7 r7 x t8 a: S& U& b- E0 W
134439 PD-COMPILE USERDATA caCell terminals should be top-levelterminals
- d' N0 ~6 N) l' r x# N( W186074 CIS EXPLORER refresh symbols from lib requires youto close CIS
) Y5 C" ~0 }# _( U' _, w$ ?583221 CAPTURE SCHEMATIC_EDITOROption to have the Schematic Page Name as a Property in the Titleblock
" }- V9 ]2 }* D. `, q) ]+ ?591140 concept_HDL OTHER Scale overall output size inPublishPDF from command line7 @) I) J( b* [8 E5 M6 y
801901 CONCEPT_HDL CORE Concept Menus use the same key"R" for the Wire and RF-PCB menus- H$ J' x( l; G# ]/ o" Y. u7 N
813614 APD DRC_CONSTRAINTS With Fillets present the "cline toshape" spacing is wrong.
9 c& c( f* \! U3 {881796 ALLEGRO_EDITOR GRAPHICS Enhancement request for Panning with Middle Mouse Button3 e7 b* C9 E4 R+ }) I. G+ f
887191 CONCEPT_HDL CORE Cannot add/edit the locked property
& Q8 [. X* y& E2 V7 m! v911292 CONCEPT_HDL CORE Property command on editing symbolattaches property to ORIGIN immediately
% S& t* s3 m1 P3 B987766 APD SHAPE Void all command gets result as novoids being generated on specific env.* B5 I; I4 V. e2 R8 X; E, `9 J
1001395 SIP_LAYOUT ASSY_RULE_CHECK Shape Minimumvoid check reports lots of DRCs which are not necessary to check out.
$ i1 ]! V3 k/ n# I1030696 ALLEGRO_EDITOR INTERACTIV Enh - Allow another behavior of PANmovement using middle mouse in Allegro
2 p* h, Q* T+ f$ f( K0 k1043856 ADW TDA Diff between TDOand DE-HDL Hierarchy Viewer is confusing to the user
2 e8 l) P+ ^: k. r% ]) b1046440 ADW PCBCACHE ADW: ImportSheetis not caching libraries under flatlib/model_sym when the source design is notan ADW project
) m; n$ b/ _, r1077552 F2B PACKAGERXL Diff Pairs get removed when packing withbackannotation turned on5 Q% b5 X& I7 }- P% k4 j* S6 k
1079538 F2B PACKAGERXL Ability to blockall 縮ingle noded nets� to the board while packaging.
/ }3 Y3 R% [% k: g3 W7 b* w, P1086362 ALLEGRO_EDITOR SHAPE Enhancement request to autovoid a viaif shape cannot cover the center of the via.
j& o: x f0 d0 `, p# S( y1087958 Pspice MODELEDITOR Is there anylimitation for pin name definition?, n8 g% @9 y* S2 M) Q: K! j, Z
1087967 CIS UPDATE_PART_STAT Update part status window shows incorrect differences
$ ~1 m2 X8 B7 c1090693 ADW LRM LRMauto_load_instances does not gray out Load instances Button! x! _- @) ~5 [: X t
1097246 CONCEPT_HDL CORE ConceptHDL -assign hotkeys to alpha-numerical keys) O( @+ @( x0 L9 n5 m
1099773 CONCEPT_HDL CORE DE HDL goes intorecursive loop if a custom text locked at site level is deleted from Tools >Option& p& H5 W& g# R% D
1100945 SCM SCHGEN SCM generatedDE-HDL has $PN placement issue' x U/ U! ]7 M! v6 `2 b7 X3 u
1100951 PSPICE SIMULATOR Increasing theresolution of fourier transform results in out file* z5 P( g$ o, y* `+ n
1103117 RF_PCB FE_IFF_IMPORT Enh- Allow theAllegro_Discrete_Library_to_ADS_Library_Translator to output in its originalunit
e6 I" z9 n6 s* Q, P2 ^3 N5 b$ P% E1105473 PSPICE PROBE Getting errormessages while running bias point analysis./ y. Y3 |# c! n |
1106116 FLOWS PROJMGR view_pcb settingchange was cleared by switching Flows in projmgr.; ~. c7 i8 a2 i+ a3 ]0 s
1106298 ALLEGRO_EDITOR INTERACTIV Copy Shape uses last menu pick locationas origin and not the Symbol Origin as specified in Options.
: t7 ]. {3 c% u. A5 @$ z. ^2 {1106626 CONCEPT_HDL CORE Concept HDL crashes when saving pages
. G- }* t0 G' M% `; v1107086 ALLEGRO_EDITOR INTERACTIV manual void with arc's goes in wrongdirection during arc creation
0 ^, I% o! z, f& m4 C, @$ {$ m1 O1107172 CONCEPT_HDL OTHER Project ManagerPackager does not report errors on missing symbol0 f6 O9 U4 O8 P) h& Q
1108193 CONCEPT_HDL CORE Using theleft/right keys do not move the cursor within the text you're editing( G, v( J* y5 Z r! T
1108603 PCB_LIBRARIAN VERIFICATION PDV ToolsVerification > View Verification (CheckPlus) leaves<project>.cpm_tmp.cpm$ s/ b& J* Z2 Z8 t$ I
1109024 CIS OTHER orcad performance issue from Asus.3 t% x7 ?$ T" A+ `- ]
1109109 CAPTURE NETLIST_ALLEGRO B1: Netlistmissing pins when Pack_short property pins connected
8 R* U) M4 s* ]7 G3 R1109466 ALLEGRO_EDITOR ARTWORK Artwork create some strange gerberlines for fillet.% S9 S0 D2 W- x7 G4 e' r
1109647 SIP_LAYOUT DEGASSING Shape degassingcommand enhancement - control over what layers are counted in even/odd layersets.0 D% h* U* k C7 U
1109926 CONCEPT_HDL CORE viewing a designdisables console window
! ? V a# n! ` Y9 D! f. F1110194 SIP_LAYOUT WIREBOND If OpenGL settings for display ofdynamic net names is enabled, should be visible while push/shove wirebonds.
" Q$ A+ y2 K- @! T, \) d$ D1112357 SIP_LAYOUT WIREBOND wirebond commandcrashes the application
0 z3 ~0 P n' G) K* x% m, A& @1112395 CONCEPT_HDL CORE 縗BASE\G� for global signal is not obeyedafter upreving the design to 1650.
" q0 I+ c: h- Q7 t# @1112658 CAPTURE PROPERTY_EDITOR Changing Part 縂raphic� value from property EditorChanges Occ refdes values to instance* L4 y; J; `: I- l0 Y% C3 H
1112662 CAPTURE PROJECT_MANAGER Capture crashesafter moving the library file and then doing Edit> Cut
; r+ P7 N4 K1 s7 a- W1113177 PCB_LIBRARIAN CORE Pin Shapes arenot getting imported properly* K O. v7 Q, `
1113380 ALLEGRO_EDITOR INTERACTIV Change layer to - option for packagetype .dra is not available in 16.6 release2 q- q: ~. \/ W) Q5 ^% G4 @
1113656 SIP_LAYOUT WIREBOND Enable Changecharacteristic to work without unfixing its Tack point.$ ~% e- V p) l. w
1113838 SIP_LAYOUT DIE_ABSTRACT_IF probe pinsdefined in XDA die abstract file are added with wrong location% d% S3 N3 ^, d! {3 F: u% u' v" O/ V
1113991 CAPTURE GENERAL Save Project Asis not working if destination is a linux machine
* I3 }4 v" r; F1114073 APD DRC_CONSTRAINTS Shape voidingdifferently if there are Fillets present in the design." ?/ _ g: G3 j. D( W
1114241 CAPTURE SCHEMATIC_EDITOR Port not retaining assigned color, when moved on theschematic
5 Y0 W/ R8 T, |$ s8 W1114442 PSPICE PROBE Getting Internalerror - Overflow Convert with marching waveform on
5 v5 k/ d2 z, X' v1114630 CONCEPT_HDL ARCHIVER Archcore failsbecause the project directory on Linux has a space in the name( O8 ^$ C/ Y7 \ p7 \# e- b+ \# g
1114689 CONCEPT_HDL CORE Unknown projectdirective : text_editor( e# }+ t* ?! q$ z# N7 f
1114928 F2B PACKAGERXL 縀rror (SPCODD - 5) while Export Physical even afterchange pin from A<0> to A+ v, x) K w, ]$ p; S
1116886 CONCEPT_HDL CORE Crefer hyperlinksdo not work fine when user use double digits partitions for page Border.
% b# I, @* \; X1118088 ALLEGRO_EDITOR EDIT_ETCH Should Plan accurate and Optimize beremoved in 16.6?
8 D3 D+ v- J" R1118734 APD EDIT_ETCH Multiline routingwith Clines on Null Net cannot route in downward direction
) N: n" O2 V! s9 h$ n$ S7 Y1118756 ALLEGRO_EDITOR SHAPE Shape clearance parameter oversizevalues getting applied to Keepouts
9 E( j2 V0 [% u5 L3 T- r1119606 CONCEPT_HDL MARKERS Filtering two ormore words in Filter dialog box
0 }5 S# ]% a2 _5 ^6 s4 g; n1119707 CONCEPT_HDL CORE Genview does not use site colors when gen schfrom block symbol" ]0 J$ _( R2 p2 k. }* N) v
1119711 F2B DESIGNSYNC DesignDifferences show Net Differences wrongly6 a, n! P3 s* S
1120659 CAPTURE PROJECT_MANAGER "Saveproject as" does not support some of Nordic characters.9 b( d2 w0 ]. b4 e1 [5 t4 L
1120660 CONCEPT_HDL CORE Save hierarchysaves pages for deleted blocks.6 r! r. O/ y7 k, z3 K" r
1120817 SIP_LAYOUT SYMB_EDIT_APPMOD Rotate pads commands not working while in the SymbolEdit App. mode$ T1 W* T8 O$ O
1120985 PSPICE MODELEDITOR Unable to importattached IBIS model- F: B# |+ q8 W8 ~
1121171 CONCEPT_HDL CREFER PNN and correctproperty values not annotated on the Cref flat schematic8 U+ E, h) l& }/ y* b
1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change aftersaving and reopening.6 y& i3 A& |, I! R+ O' M) h/ E
1121382 ALLEGRO_EDITOR INTERACTIV Undo command is limited to two for thisdesign; i; ]' {* I" A ^' G+ S$ y7 C! ?
1121540 F2B PACKAGERXL pxl.chg keepsdeleting and adding changes on subsequent packager runs
% R" K' |) s; E* ?! _4 k9 j* n" L1121558 ALLEGRO_EDITOR MODULES Unrouted net and unrouted connectionwhen module is placed of completely routed board file. [3 p6 W' v; R9 L* |
1121585 ALLEGRO_EDITOR OTHER Drill Hole to Shape Same NetSpacing with Dynamic Shapes shows wrong result.: a b0 ]* I2 \# K9 h3 _2 v# }
1121651 CAPTURE SCHEMATIC_EDITOR "PCB editor select" menu option is missing# \! u* j0 v" `% K! O( S
1122136 SIP_LAYOUT PLACEMENT Moving acomponent results in the components outline going to bottom side of the design.7 }# u7 Z$ a( }" L+ U
1122340 CAPTURE NETLIST_ALLEGRO Cross probe ofnet within a bus makes Capture to hang.
% q2 ^' L$ G$ V% p9 i3 i$ V$ o1122489 CONCEPT_HDL OTHER Save _Hierarchycausing baseline to brd files+ p+ c: b$ R9 ]4 D
1122781 CONCEPT_HDL CORE cfg_package isgenerated for component cell automatically
# R. P# L8 x; a% {) q9 a1122909 CONCEPT_HDL CORE changing versionreplicates data of first TOC on 2nd one! i, W0 `1 A1 h& [' b3 E
1123150 CONCEPT_HDL CORE property on yaxis in symbol view was moved by visibility change to None.
5 D2 ^1 P/ b' Z q1123176 ALLEGRO_EDITOR UI_FORMS Negative values for pop-up location isnot retained with multiple monitors (more than 2); k, C# n7 a0 Z- H; V
1123815 ALLEGRO_EDITOR GRAPHICS Embedded netname changes to a differentnetname
! m5 L& v/ j! P, P) T1124369 ALLEGRO_EDITOR INTERACTIV Sliding a shape using iy coordinate doesnot work indepedent of grid.
: q3 P D) ]* k: f- }3 S1124544 CONCEPT_HDL CORE About SearchHistory of find with SPB16.56 L' h# D) t7 | |! \
1124570 APD IMPORT_DATA When importingStream adding the option to change the point q$ j3 _( m, a9 k2 y
1125201 CONCEPT_HDL CORE Connectivityedits in NEW block not saved( lost) if block is created using block add
# O1 x1 \" z& n% H1125314 ALLEGRO_EDITOR INTERACTIV Enved crash during setting of library paths inuser preference0 \0 Z! [4 ^8 _. \2 [: [
1125366 CONCEPT_HDL CORE DE-HDL crachESDuring Import Physical if CM is open on Linux
6 f% j" T: c9 f$ u6 p) p8 N% m1125628 CONCEPT_HDL CORE Crash on doingsave hierarchy
$ a; p! a! q5 T- i6 d; W5 \8 |1130555 APD WIREBOND Wirebond Import should connect to pinsof the die specified on the UI.
- A- A, n* n$ @+ }3 r1131030 PSPICE ENVIRONMENT Unregistered iconof Simulation setting in taskbar
3 a) h4 h2 b. K2 b* j1131083 ALLEGRO_EDITOR INTERACTIV Bug: 16.6 crash in changing the mode inFind filter window- ^ j& x4 J, I& l! Z" c
1131226 ALLEGRO_EDITOR PLACEMENT When Angle is set in design parameterswhile placement component is rotated but outline is not.
, c! v" O D/ C* K0 r& X) [% R1131567 CONCEPT_HDL OTHER Lower case valuesfor VHDL_MODE make genview use pin location to determen direction.% U5 q3 a2 M; t! \; k( o6 L! G+ K
1131699 PSPICE PROBE Probe windowcrash on trying to view simulation message
! ~0 l- q; s+ N& [( l1132457 CONCEPT_HDL CORE The schematicnever fully invokes and has connectivity errors.
6 M+ p6 h, D2 F! E1132575 CONCEPT_HDL CORE 2 pin_name weredisplayed and overlapped by spin command.2 J; ]) ^$ v0 ^( P& y: Y6 p) @$ M
1132698 ALLEGRO_EDITOR EDIT_ETCH Slide Via with Segment option with newSlide command0 e: F0 M$ @2 m/ R5 B
1132964 ALLEGRO_EDITOR SHAPE Same net "B&B via toshape" errors created when adding shape* N4 }1 Q/ e+ P, K( M
1133677 CONCEPT_HDL CORE Cant delete norreset LOCATION prop in context of top
$ K; i6 ~/ J; b' |3 v7 Y/ d& o( b- X1133791 CONCEPT_HDL CORE Cant do textjustification on a single selected NOTE in Windows mode.' R2 v3 W3 a) W8 B* a
1134761 CONCEPT_HDL CORE Why does MousePointer/Tooltip display LOCATION instead of $LOCATION property
, @% e1 M+ H' |" k/ h! q1135118 ALLEGRO_EDITOR INTERACTIV Mirror and other editing commands aremissing for testpoint label text in general edit mode.( C# j* Y w8 }4 Z7 I" j
1136420 CAPTURE GENERAL Registrationissue when CDSROOT has a space in its path
, r* c; z& I% I8 H7 Z' ]7 o1136808 PSPICE STABILITY Pspice crashmarker server has quite unexpectedly" ^% A. x) T Z" T1 p: Z( t
1136840 CAPTURE SCHEMATICS Enh: Alignment oftext placed on schematic page
" S6 {7 O9 H( t/ C1 u7 X1138586 ADW MIGRATION design migrationdoes not create complete ptf file for hierarchical designs
\9 F5 G1 V; }/ b1139376 CONCEPT_HDL CORE setting wirecolor to default creates new wire with higher thickness0 [9 L% c! e2 {
1140819 APD GRAPHICS Bbvia does notretain temp highlight color on all layers when selected.
/ p! K6 x w' T0 |* L X/ s0 o. |1141300 CONCEPT_HDL CORE DE HDL hier_writesave hierarchy log reports summarizes Successfully saved block x while blockwas skipped7 B) d: _7 V4 X# V) r
1141723 ADW PURGE purge commandcrashes with an MFC application failure message2 @# ?, W/ q& c: y9 y3 R4 k
1143448 CAPTURE GENERAL About copy &paste to Powerpoint from CIS1 Q4 x G8 V! ~+ T, E2 q) h
1143670 SIP_LAYOUT OTHER Cross Probingbetween SiP and DEHDL not working in 16.6 release
2 F7 g6 F/ i# Q7 {1143902 ALLEGRO_EDITOR DATABASE when the shape is rotated 45 degreesthe void is moved.: @# p# Y7 h3 d: s/ f1 Z' c$ d
1144990 PCB_LIBRARIAN CORE PDV expand &collapse vector pins resizes symbol outline to maximum height
: [! g/ \5 [' Z2 j3 f! y+ ?6 `- H1145112 CONCEPT_HDL CORE Warning message:Connectivity MIGHT have changed
2 K$ k/ j( |7 Q1 J: t6 A1145253 CONCEPT_HDL CORE Component Browseradds properties in upper case
, k, Y. K% f' T$ g7 }1146386 ALLEGRO_EDITOR INTERACTIV Place Replicate Create add Static shapewith Fillet shape. Z7 O! N2 B7 w8 v
1146728 F2B PACKAGERXL DCF with upperand lower case values on parts causes pxl to fail
( W' b* t# r- E2 S& m# a5 H1146783 ALLEGRO_EDITOR INTERFACES Highlighted component is missing fromexported IPF file.) w: i5 _! K: G0 ]
1147326 CONCEPT_HDL CORE HDL crashes whentrying to reimport a block3 ]* z" @+ J4 H1 F
1148337 CAPTURE ANNOTATE Checking "refdes control" isnot giving the proper annotation result/ s" N3 l3 G/ v+ C j) s" b7 |
1148633 SIP_LAYOUT INTERACTIVE Add "%"to the optical shrink option in the co-design die and compose symbol placementforms
/ I* @( d. i8 Q* }% Z7 E! w1 H1149778 CAPTURE SCHEMATICS Rotation of pspice marker before placementis not appropriate
# [, C; X+ X% O- B1149987 PCB_LIBRARIAN PTF_EDITOR Save As pushingthe part name suffix into vendor_part_number value
7 Y- m" r: F T' e( A0 ~1151748 ALLEGRO_EDITOR OTHER If the pad and cline are the samewidth don't report a missing Dynamic Fillet.9 H8 C4 s+ V3 ~9 b0 a `# r
1152206 CONCEPT_HDL CORE ROOM Propertyvalue changes when saving another Page4 o% ^9 I, N9 F8 a" q$ p
1152755 CONCEPT_HDL COPY_PROJECT Copy projecthangs if library or design name has an underscore( l! |% y3 r8 P& o
1152769 PSPICE ENCRYPTION Unable to simulate Encrypted Models in16.6
' M8 w4 M- t& t4 I, C1153308 ALLEGRO_EDITOR DRC_CONSTR Creating Artwork Getting Warning"DRC is out of Date" even when DRC is up to date
, c# D. |* H+ I2 T- W; H* s1153893 F2B DESIGNVARI 16.6 VariantEditor not supporting - in name& M# Q; E) h, I% J& q
1154185 SIG_INTEGRITY SIGNOISE Signoise didn'tdo the Rise edge time adjustment.
! H$ c. Z2 Q5 |1154860 ALLEGRO_EDITOR MANUFACT Double digit drill character overlapswith figures triangle, hexagon and octagon in NC drill legend# F# g5 x* X" o; v7 D
1155167 ALLEGRO_EDITOR EDIT_ETCH Via structure placed in Create Fanouthas incorrect rotation.8 u8 B4 i l0 X/ b# x& e: H
1155728 CONCEPT_HDL CORE Unable to uprevpackaged 16.3 design in 16.5 due to memory2 ?# D" I6 [' _# _& b/ E$ [0 _
1155855 SCM SCHGEN A newlyuser-defined net property is not transferred from SCM to DEHDL in PreservedMode3 w }: k) |+ G' O, B
1156274 ALLEGRO_EDITOR INTERFACES Exported Step file from Allegro is wrong
3 M) w" n' `6 x+ e7 @0 n1 M" E0 I" F1156316 CONSTRAINT_MGR OTHER Break in functionality whilecreation of pin-pairs under Xnet in Constraint Manager* N j: ]1 k$ m) ~) x
1156351 CONCEPT_HDL CONSTRAINT_MGR Loose members inPhysical Net Class between DEHDL and Allegro, z8 b _4 I% }9 Z
1156547 ALLEGRO_EDITOR DRC_CONSTR Etch Turn under SMD pin rule checkthrough pin Etch makes confused.
* A* y- h4 o, E" I0 [' S; O, E1156779 CONSTRAINT_MGR OTHER Electrical Cset References in CM notworking correctly3 l! P3 U+ i% I: n' F3 J! w6 N* p
1157167 ALLEGRO_EDITOR skill axlPolyFromDB with ?line2poly isbroken" j* ]& y) b8 S% {
1158042 ALLEGRO_EDITOR DFA DFA_DLG writes the dra file namein uppercase.
" @: w$ U- k2 p* g2 X1158718 CONCEPT_HDL CHECKPLUS Customer couldnot get $PN property values on logical rule of CheckPlus16.6.& R* A o2 L' T: s! n
1158970 ALLEGRO_EDITOR SCHEM_FTB Changing LOCATION to $LOCATION in DEHDLdoes not update the .brd file
" q/ H4 y" u J: n3 I' ?5 {1158989 ALLEGRO_EDITOR INTERFACES pdf_out -l creates a PDF6 Z1 x9 y) |. U! R6 H% `2 I; ]7 d
1159285 APD DXF_IF DXF_OUT fails;some figures are not exported
7 c8 T, L @$ e+ B7 @7 \) X3 l1159432 ALLEGRO_EDITOR SHOW_ELEM http:// in the Show Element in 166 donot have HTML link to open the Website# n5 D' @4 {5 `; r
1159483 PCB_LIBRARIAN SETUP part developercrashing with
' c8 _$ g2 v: H: ?0 T. J: K1159516 ALLEGRO_EDITOR EDIT_ETCH Unable to slide cline segment with newslide.
+ S# n! [( v5 l3 M1159959 ALLEGRO_EDITOR GRAPHICS 3D viewer displays clines arcsincorrectly/ A) D- w9 K! \* h% d! Q
1160004 SCM UI The RMB->Pastedoes not insert signal names.
4 A$ T1 O/ c$ ~4 O' @# R1160410 ALLEGRO_EDITOR DATABASE Lock databse with View Lock option ismisleading
i, `0 L- e) P* U1160529 SCM SCHGEN Schematicgeneration stopped because the tool was unable to create an appropriateinternal symbol structure) G: n; j @7 k0 J7 n
1160537 SPIF OTHER Cannot start PCBRouter4 |# ]. Q+ F& m9 d: G- u! B0 j' g
1161363 ALLEGRO_EDITOR SYMBOL Getting error SPMHGE-73 when tryingto mirror symbol5 e! \, w. Q2 o
1161781 CONSTRAINT_MGR CONCEPT_HDL SigXp crash when selecting ECset indesign
e4 ?- g: } W; L2 e; q+ F1161896 ALLEGRO_EDITOR DRAFTING Tolerance value added for Dimensionsis not working correctly (HF11-12)# z5 u1 {5 H; [% K6 g. ?- Q4 g# f+ m
1162193 SIP_LAYOUT DIE_ABSTRACT_IF shapes in diafile not linked to the die after edit co-design die
8 E4 v7 u% ^! R' n6 k6 I5 E1162754 APD VIA_STRUCTURE Replace Via Structurecommand selecting dummy nets. |
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发表于 2013-8-5 10:07
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