Cadence SPB16.6下载(Hotfix013已发布更新)

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cadence SPB16.6下载(Hotfix013已发布)

Cadence SPB16.6已经推出，需要的朋友可以点击下面的链接下载：
' p& B+ ]8 d- N* _0 `5 thttp://dl.vmall.com/c0ych9k8m3

9 _! X8 u! j0 a/ b: w& E+ RDATE: 07-26-2013  HOTFIX VERSION: 013
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  h+ |6 e3 ]6 ^- R% FCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
111368 CAPTURE        CORRUPT_DESIGN   Capture - will not produce allegro netlistwith 10.0
6 c! k4 V! X+ [( t2 |% K( s134439 PD-COMPILE     USERDATA         caCell terminals should be top-levelterminals
186074  CIS            EXPLORER         refresh symbols from lib requires youto close CIS
5 T# A- X7 h: y" y- B) p583221 CAPTURE        SCHEMATIC_EDITOROption to have the Schematic Page Name as a Property in the Titleblock
; X) D8 w$ B3 Y5 n% b591140 concept_HDL    OTHER            Scale overall output size inPublishPDF from command line
# _- h3 _4 {" k" D801901 CONCEPT_HDL    CORE             Concept Menus use the same key"R" for the Wire and RF-PCB menus
813614  APD            DRC_CONSTRAINTS  With Fillets present the "cline toshape" spacing is wrong.
# i" `4 E: U6 f2 q6 ~( n881796 ALLEGRO_EDITOR GRAPHICS        Enhancement request for Panning with Middle Mouse Button
6 S, I% N! G; Y/ |: i887191 CONCEPT_HDL    CORE             Cannot add/edit the locked property
4 P# I( d  w" j' x" C5 H& ]6 J9 s911292 CONCEPT_HDL    CORE             Property command on editing symbolattaches property to ORIGIN immediately
$ J/ C. j. L: n/ m9 W3 c987766  APD            SHAPE            Void all command gets result as novoids being generated on specific env.
1001395 SIP_LAYOUT    ASSY_RULE_CHECK  Shape Minimumvoid check reports lots of DRCs which are not necessary to check out.
1030696 ALLEGRO_EDITOR INTERACTIV       Enh - Allow another behavior of PANmovement using middle mouse in Allegro
1043856 ADW           TDA              Diff between TDOand DE-HDL Hierarchy Viewer is confusing to the user
1046440 ADW           PCBCACHE         ADW: ImportSheetis not caching libraries under flatlib/model_sym when the source design is notan ADW project
1077552 F2B           PACKAGERXL       Diff Pairs get removed when packing withbackannotation turned on
1079538 F2B           PACKAGERXL       Ability to blockall 縮ingle noded nets� to the board while packaging.
1086362 ALLEGRO_EDITOR SHAPE            Enhancement request to autovoid a viaif shape cannot cover the center of the via.
  @& u! [0 H: Y1087958 Pspice        MODELEDITOR      Is there anylimitation for pin name definition?
) o  a+ _- x. X' d2 H5 F1087967 CIS           UPDATE_PART_STAT Update part status window shows incorrect differences
* I) {4 g0 i( C" P# w1 o1090693 ADW           LRM              LRMauto_load_instances does not gray out Load instances Button
1097246 CONCEPT_HDL   CORE             ConceptHDL -assign hotkeys to alpha-numerical keys
9 a# C' P: i/ Z1 |8 E. l, r1099773 CONCEPT_HDL   CORE             DE HDL goes intorecursive loop if a custom text locked at site level is deleted from Tools >Option
% V$ a* d  w" g/ M% v1100945 SCM           SCHGEN           SCM generatedDE-HDL has $PN placement issue
( P: T3 w2 w2 }+ w1 L6 G1100951 PSPICE        SIMULATOR        Increasing theresolution of fourier transform results in out file
1103117 RF_PCB        FE_IFF_IMPORT    Enh- Allow theAllegro_Discrete_Library_to_ADS_Library_Translator to output in its originalunit
. b' ^5 g3 M9 t1105473 PSPICE        PROBE            Getting errormessages while running bias point analysis.
" w3 t$ \. i9 m+ v" ?1106116 FLOWS         PROJMGR          view_pcb settingchange was cleared by switching Flows in projmgr.
# P2 n( H: w& N; {* z1106298 ALLEGRO_EDITOR INTERACTIV       Copy Shape uses last menu pick locationas origin and not the Symbol Origin as specified in Options.
7 R8 }# n* }& I) n5 h5 G! m( Z1106626 CONCEPT_HDL   CORE             Concept HDL crashes when saving pages
( E8 |1 E4 H  q% P. }0 s1107086 ALLEGRO_EDITOR INTERACTIV       manual void with arc's goes in wrongdirection during arc creation
: p8 S. X* ?* ]# H% }0 T+ g1107172 CONCEPT_HDL   OTHER            Project ManagerPackager does not report errors on missing symbol
1108193 CONCEPT_HDL   CORE             Using theleft/right keys do not move the cursor within the text you're editing
$ e( h) V* c) ?! z: u, f1108603 PCB_LIBRARIAN VERIFICATION     PDV ToolsVerification > View Verification (CheckPlus) leaves<project>.cpm_tmp.cpm
1109024 CIS            OTHER            orcad performance issue from Asus.
/ Y- d* `7 |6 R1 n1109109 CAPTURE       NETLIST_ALLEGRO  B1: Netlistmissing pins when Pack_short property pins connected
1 b+ w2 k  J' j3 R7 l; L. G1109466 ALLEGRO_EDITOR ARTWORK          Artwork create some strange gerberlines for fillet.
$ p4 e8 s$ H/ X6 f% G1109647 SIP_LAYOUT    DEGASSING        Shape degassingcommand enhancement - control over what layers are counted in even/odd layersets.
1109926 CONCEPT_HDL   CORE             viewing a designdisables console window
1110194 SIP_LAYOUT    WIREBOND         If OpenGL settings for display ofdynamic net names is enabled, should be visible while push/shove wirebonds.
5 b' u9 i8 J1 V: @- [2 x1112357 SIP_LAYOUT    WIREBOND         wirebond commandcrashes the application
. d5 F, @2 s5 S! u& _1 H- [7 K4 K1112395 CONCEPT_HDL   CORE             縗BASE\G� for global signal is not obeyedafter upreving the design to 1650.
1112658 CAPTURE       PROPERTY_EDITOR  Changing Part 縂raphic� value from property EditorChanges Occ refdes values to instance
4 G* I: W0 k9 {% v1112662 CAPTURE       PROJECT_MANAGER  Capture crashesafter moving the library file and then doing Edit> Cut
1 k2 Z+ ^0 l0 r1113177 PCB_LIBRARIAN CORE             Pin Shapes arenot getting imported properly
1113380 ALLEGRO_EDITOR INTERACTIV       Change layer to - option for packagetype .dra is not available in 16.6 release
1 p% V; @+ D4 ^& W1113656 SIP_LAYOUT    WIREBOND         Enable Changecharacteristic to work without unfixing its Tack point.
1113838 SIP_LAYOUT    DIE_ABSTRACT_IF  probe pinsdefined in XDA die abstract file are added with wrong location
1113991 CAPTURE       GENERAL          Save Project Asis not working if destination is a linux machine
. O% u  B: n$ a6 @4 ]' B1114073 APD           DRC_CONSTRAINTS  Shape voidingdifferently if there are Fillets present in the design.
& T( _2 m& z1 \( m/ w1114241 CAPTURE       SCHEMATIC_EDITOR Port not retaining assigned color, when moved on theschematic
1114442 PSPICE        PROBE            Getting Internalerror - Overflow Convert with marching waveform on
6 w7 m# }7 Y& v' o, K5 E& k6 c1114630 CONCEPT_HDL   ARCHIVER         Archcore failsbecause the project directory on Linux has a space in the name
! K) P4 o2 f0 e# @1 ^1114689 CONCEPT_HDL   CORE             Unknown projectdirective : text_editor
1114928 F2B           PACKAGERXL       縀rror (SPCODD - 5) while Export Physical even afterchange pin from A<0> to A
1116886 CONCEPT_HDL   CORE             Crefer hyperlinksdo not work fine when user use double digits partitions for page Border.
" |: v; P8 ^2 d/ [  F4 X, @( E1118088 ALLEGRO_EDITOR EDIT_ETCH        Should Plan accurate and Optimize beremoved in 16.6?
2 ?5 n& V; Z, c  J1118734 APD           EDIT_ETCH        Multiline routingwith Clines on Null Net cannot route in downward direction
1118756 ALLEGRO_EDITOR SHAPE            Shape clearance parameter oversizevalues getting applied to Keepouts
9 {* t% |4 d$ E, g7 V1119606 CONCEPT_HDL   MARKERS          Filtering two ormore words in Filter dialog box
1119707 CONCEPT_HDL   CORE             Genview does not use site colors when gen schfrom block symbol
  J6 t1 p# p/ B1119711 F2B           DESIGNSYNC       DesignDifferences show Net Differences wrongly
# ]" f* `2 E7 `1120659 CAPTURE       PROJECT_MANAGER  "Saveproject as" does not support some of Nordic characters.
$ Y5 g3 z/ k" d7 S/ D* \! {! x1120660 CONCEPT_HDL   CORE             Save hierarchysaves pages for deleted blocks.
1120817 SIP_LAYOUT    SYMB_EDIT_APPMOD Rotate pads commands not working while in the SymbolEdit App. mode
1120985 PSPICE        MODELEDITOR      Unable to importattached IBIS model
5 d! C" g  o# ?& ]- q( r$ R1121171 CONCEPT_HDL   CREFER           PNN and correctproperty values not annotated on the Cref flat schematic
3 i+ ]+ r  ^8 j4 s3 Z% \) ~1121353 ALLEGRO_EDITOR INTERACTIV       Local env setting will change aftersaving and reopening.
, X5 G; x/ O1 \9 l3 T5 `0 ~) @4 w1121382 ALLEGRO_EDITOR INTERACTIV       Undo command is limited to two for thisdesign
% Q6 q' b* N# f9 G" W3 W0 @1121540 F2B           PACKAGERXL       pxl.chg keepsdeleting and adding changes on subsequent packager runs
1121558 ALLEGRO_EDITOR MODULES          Unrouted net and unrouted connectionwhen module is placed of completely routed board file.
2 m9 b# }& D0 p5 B' S4 ~1121585 ALLEGRO_EDITOR OTHER            Drill Hole to Shape Same NetSpacing with Dynamic Shapes shows wrong result.
8 W' r6 ?* Q/ y( q( }1121651 CAPTURE       SCHEMATIC_EDITOR "PCB editor select" menu option is missing
6 \) `% |3 Z$ D6 I6 C9 l1122136 SIP_LAYOUT    PLACEMENT        Moving acomponent results in the components outline going to bottom side of the design.
1122340 CAPTURE       NETLIST_ALLEGRO  Cross probe ofnet within a bus makes Capture to hang.
1122489 CONCEPT_HDL   OTHER            Save _Hierarchycausing baseline to brd files
4 X0 v, j1 v% I  m" B! X  t: m1122781 CONCEPT_HDL   CORE             cfg_package isgenerated for component cell automatically
4 m( h% \  P& o, Z2 w, T' j1122909 CONCEPT_HDL   CORE             changing versionreplicates data of first TOC on 2nd one
' Y$ C- N% |# k1 ^- @! J8 c1123150 CONCEPT_HDL   CORE             property on yaxis in symbol view was moved by visibility change to None.
1123176 ALLEGRO_EDITOR UI_FORMS         Negative values for pop-up location isnot retained with multiple monitors (more than 2)
1123815 ALLEGRO_EDITOR GRAPHICS         Embedded netname changes to a differentnetname
1124369 ALLEGRO_EDITOR INTERACTIV       Sliding a shape using iy coordinate doesnot work indepedent of grid.
" Z6 E3 M# \1 q; d! X8 a/ I1124544 CONCEPT_HDL   CORE             About SearchHistory of find with SPB16.5
1124570 APD           IMPORT_DATA      When importingStream adding the option to change the point
3 X* t! L9 H0 b6 \+ F# w1125201 CONCEPT_HDL   CORE             Connectivityedits in NEW block not saved( lost) if block is created using block add
1125314 ALLEGRO_EDITOR INTERACTIV       Enved crash during setting of library paths inuser preference
. H3 Z, @3 B9 @" m) P1125366 CONCEPT_HDL   CORE             DE-HDL crachESDuring Import Physical if CM is open on Linux
; E# a/ v0 w, C: n$ l) W- b& u1125628 CONCEPT_HDL   CORE             Crash on doingsave hierarchy
1130555 APD           WIREBOND         Wirebond Import should connect to pinsof the die specified on the UI.
1131030 PSPICE        ENVIRONMENT      Unregistered iconof Simulation setting in taskbar
* R# {: L  ^7 D0 X% S" p) }8 A* S1131083 ALLEGRO_EDITOR INTERACTIV       Bug: 16.6 crash in changing the mode inFind filter window
) a4 V6 O: Y% C2 E1131226 ALLEGRO_EDITOR PLACEMENT        When Angle is set in design parameterswhile placement component is rotated but outline is not.
1131567 CONCEPT_HDL   OTHER            Lower case valuesfor VHDL_MODE make genview use pin location to determen direction.
  L* u# }  G2 T1131699 PSPICE        PROBE            Probe windowcrash on trying to view simulation message
6 ]8 m) Y6 Q% P. ~, Y+ e1132457 CONCEPT_HDL   CORE             The schematicnever fully invokes and has connectivity errors.
! s6 j. e: B5 ?4 _5 S1132575 CONCEPT_HDL   CORE             2 pin_name weredisplayed and overlapped by spin command.
1132698 ALLEGRO_EDITOR EDIT_ETCH        Slide Via with Segment option with newSlide command
1132964 ALLEGRO_EDITOR SHAPE            Same net "B&B via toshape" errors created when adding shape
0 Z9 w) V& k( I1 I- ~5 g3 ~1133677 CONCEPT_HDL   CORE             Cant delete norreset LOCATION prop in context of top
1133791 CONCEPT_HDL   CORE             Cant do textjustification on a single selected NOTE in Windows mode.
) R# H# [, }, V% V/ b% {, \( \1134761 CONCEPT_HDL   CORE             Why does MousePointer/Tooltip display LOCATION instead of $LOCATION property
4 h$ b4 B. a* N1135118 ALLEGRO_EDITOR INTERACTIV       Mirror and other editing commands aremissing for testpoint label text in general edit mode.
& g: m7 m2 k% u1136420 CAPTURE       GENERAL          Registrationissue when CDSROOT has a space in its path
0 G; m- K3 f4 g5 p/ i( o1136808 PSPICE        STABILITY        Pspice crashmarker server has quite unexpectedly
  D: T  u4 I5 Z7 c4 p1136840 CAPTURE       SCHEMATICS       Enh: Alignment oftext placed on schematic page
1138586 ADW           MIGRATION        design migrationdoes not create complete ptf file for hierarchical designs
% Q0 Y) v+ x6 g* Y- }* `1139376 CONCEPT_HDL   CORE             setting wirecolor to default creates new wire with higher thickness
- f8 ^! r' c# O2 A, j9 R5 N0 {  b1140819 APD           GRAPHICS         Bbvia does notretain temp highlight color on all layers when selected.
2 ~" h8 d$ m3 O3 J1141300 CONCEPT_HDL   CORE             DE HDL hier_writesave hierarchy log reports summarizes Successfully saved block x while blockwas skipped
. K% c& t- z# W! u. B* z$ i1141723 ADW           PURGE            purge commandcrashes with an MFC application failure message
( F- Z. M+ f/ Q4 `" c1143448 CAPTURE       GENERAL          About copy &paste to Powerpoint from CIS
1143670 SIP_LAYOUT    OTHER            Cross Probingbetween SiP and DEHDL not working in 16.6 release
1143902 ALLEGRO_EDITOR DATABASE         when the shape is rotated 45 degreesthe void is moved.
1144990 PCB_LIBRARIAN CORE             PDV expand &collapse vector pins resizes symbol outline to maximum height
# C( H( y, h  |( `! [1145112 CONCEPT_HDL   CORE             Warning message:Connectivity MIGHT have changed
6 m, s: L1 i8 |( k1145253 CONCEPT_HDL   CORE             Component Browseradds properties in upper case
* Q# x: c1 f. P+ u1 a' m1146386 ALLEGRO_EDITOR INTERACTIV       Place Replicate Create add Static shapewith Fillet shape
1146728 F2B           PACKAGERXL       DCF with upperand lower case values on parts causes pxl to fail
7 Z; K: ], ^3 U3 ~* Z1146783 ALLEGRO_EDITOR INTERFACES       Highlighted component is missing fromexported IPF file.
& v& [% M) t& w, L" ~: n1147326 CONCEPT_HDL   CORE             HDL crashes whentrying to reimport a block
: M5 k8 B1 u5 g: ^4 q1148337 CAPTURE       ANNOTATE         Checking "refdes control" isnot giving the proper annotation result
1148633 SIP_LAYOUT    INTERACTIVE      Add "%"to the optical shrink option in the co-design die and compose symbol placementforms
1149778 CAPTURE       SCHEMATICS       Rotation of pspice marker before placementis not appropriate
1149987 PCB_LIBRARIAN PTF_EDITOR       Save As pushingthe part name suffix into vendor_part_number value
1151748 ALLEGRO_EDITOR OTHER            If the pad and cline are the samewidth don't report a missing Dynamic Fillet.
1152206 CONCEPT_HDL   CORE             ROOM Propertyvalue changes when saving another Page
1152755 CONCEPT_HDL   COPY_PROJECT     Copy projecthangs if library or design name has an underscore
0 P2 L: _6 n' u6 L' [9 }1152769 PSPICE        ENCRYPTION       Unable to simulate Encrypted Models in16.6
1153308 ALLEGRO_EDITOR DRC_CONSTR       Creating Artwork Getting Warning"DRC is out of Date" even when DRC is up to date
1153893 F2B           DESIGNVARI       16.6 VariantEditor not supporting - in name
1154185 SIG_INTEGRITY SIGNOISE         Signoise didn'tdo the Rise edge time adjustment.
1154860 ALLEGRO_EDITOR MANUFACT         Double digit drill character overlapswith figures triangle, hexagon and octagon in NC drill legend
1155167 ALLEGRO_EDITOR EDIT_ETCH        Via structure placed in Create Fanouthas incorrect rotation.
1155728 CONCEPT_HDL   CORE             Unable to uprevpackaged 16.3 design in 16.5 due to memory
1155855 SCM           SCHGEN           A newlyuser-defined net property is not transferred from SCM to DEHDL in PreservedMode
1156274 ALLEGRO_EDITOR INTERFACES       Exported Step file from Allegro is wrong
7 W8 g8 d: z- t( k) o0 o1156316 CONSTRAINT_MGR OTHER            Break in functionality whilecreation of pin-pairs under Xnet in Constraint Manager
1156351 CONCEPT_HDL   CONSTRAINT_MGR   Loose members inPhysical Net Class between DEHDL and Allegro
& b- e. v7 y  S1156547 ALLEGRO_EDITOR DRC_CONSTR       Etch Turn under SMD pin rule checkthrough pin Etch makes confused.
7 A: Z) L/ A' }: J1156779 CONSTRAINT_MGR OTHER            Electrical Cset References in CM notworking correctly
0 `( @3 M8 o3 D9 I8 m1157167 ALLEGRO_EDITOR skill            axlPolyFromDB with ?line2poly isbroken
1158042 ALLEGRO_EDITOR DFA              DFA_DLG writes the dra file namein uppercase.
8 r3 o, d8 _: |1158718 CONCEPT_HDL   CHECKPLUS        Customer couldnot get $PN property values on logical rule of CheckPlus16.6.
1158970 ALLEGRO_EDITOR SCHEM_FTB        Changing LOCATION to $LOCATION in DEHDLdoes not update the .brd file
6 f3 |3 D7 T9 x% B7 r: z3 r/ J1158989 ALLEGRO_EDITOR INTERFACES       pdf_out -l creates a PDF
# m' y4 Y8 }( u8 |* B( x& w$ S1159285 APD           DXF_IF           DXF_OUT fails;some figures are not exported
% Y' \' h0 R1 _1159432 ALLEGRO_EDITOR SHOW_ELEM        http:// in the Show Element in 166 donot have HTML link to open the Website
1159483 PCB_LIBRARIAN SETUP            part developercrashing with
6 x- M  \! X: b1159516 ALLEGRO_EDITOR EDIT_ETCH        Unable to slide cline segment with newslide.
6 _& t# S  N- c% }# ~. y1159959 ALLEGRO_EDITOR GRAPHICS         3D viewer displays clines arcsincorrectly
) R0 A( L% z2 Y* @1160004 SCM           UI               The RMB->Pastedoes not insert signal names.
. O' L) m% b, Y: H% F, J8 k1160410 ALLEGRO_EDITOR DATABASE         Lock databse with View Lock option ismisleading
6 h3 R; _; _& r& N1160529 SCM           SCHGEN           Schematicgeneration stopped because the tool was unable to create an appropriateinternal symbol structure
4 J3 |, ]6 M4 V2 J9 Q# Q# ]1 ?8 z. [1160537 SPIF          OTHER            Cannot start PCBRouter
1161363 ALLEGRO_EDITOR SYMBOL           Getting error SPMHGE-73 when tryingto mirror symbol
+ [2 P3 Y2 T% T" ^! \0 B( N1161781 CONSTRAINT_MGR CONCEPT_HDL      SigXp crash when selecting ECset indesign
1161896 ALLEGRO_EDITOR DRAFTING         Tolerance value added for Dimensionsis not working correctly (HF11-12)
4 r2 E* x! m7 A* s: E1162193 SIP_LAYOUT    DIE_ABSTRACT_IF  shapes in diafile not linked to the die after edit co-design die
: N3 B8 {# v9 W3 O1 d( Z1 v1162754 APD           VIA_STRUCTURE    Replace Via Structurecommand selecting dummy nets.

txqtomton

楼主辛苦了！ 谢谢

2000

楼主辛苦了！ 谢谢

q343408315

怎么屏蔽了

陈志军

好

每一天都不同

感谢分享